Information Technology Reference
In-Depth Information
ω
p1
= 1/[(R
s +
R
D
)C
GD
+ (R
s
+
1/ g
m
)0.5 C
GS
+ R
D
C
DB
)] . (3)
ω
p2
= 1/ K [R
s
R
D
(C
GD
C
DB +
C
GD
C
DB +
C
GD
C
DB
)] . (4)
Where, K = ( C
GD
C
DB +
C
GD
C
GS +
C
GS
C
DB
) (R
s
+
1/ g
m
) R
D +
(R
D
/ g
m
)
(C
DB +
C
GD
+
C
GS
) (C
DB +
C
GD
+
C
GS3 +
C
DB3
) +
R
D
[R
s
C
GD
(
C
GD
+ C
DB
)
+
C
DS
C
DS/
g
m
)] .
where R
S
is the resistance of the voltage sources (not shown in the figure) connected
at the inputs, the transconductance, and the capacitances are for the transistors M
1
and
M
2
(which are assumed to be identical), unless there is a subscript “3” in the name, in
which case they refer to the transistor M
3
.Comparison of Eqns. (1) and (3) shows
that the proposed architecture has a much higher dominant pole frequency,
compared to the conventional CML buffer, Moreover, due to the source-coupled
configuration of the former, two gate-source capacitances (C
GS
) are seen in series by
the input terminal, thus reducing this capacitance by a factor of 2 in the dominant pole
expression.
Design Issues
4
The load resistor R is determined by impedance matching requirements (being
typically between 50
Ω
Ω
Ω
and 100
) and was taken to be 75
. For a given
voltage swing (V
SWING
), the current I
SS
is given by I
SS
= V
SWING
/R
D
.
For the entire tail current to flow only in one branch [1],
0.5V
in
> [ 2I
SS
L / µ CoxW ]
1/2
.
(5)
from which W
1
can be calculated. Also, for keeping the current source in saturation,
V
CM
- V
GS
> V
BIAS
- V
T
.
(6)
which yields,
W
1
> 2I
SS
L / µ CoxW( V
CM
- V
BIAS
)
2
.
(7)
W
1
then must be chosen to satisfy both Eqns. (5) and (7).
