Information Technology Reference
In-Depth Information
R
S
(1 + g
m
R
D
)C
GD
+ R
S
C
GS
+ R
D
(C
GD
+ C
DB
)
ω
p2
= --------------------------------------------------------------- . (2)
R
S
R
D(
C
GD
C
DB +
C
GD
C
DB +
C
GD
C
DB
)
Due to the Miller effect, the gate-drain capacitance (C
GD
) contributes significantly
to the frequency response (through the term R
s
g
m
R
D
C
GD
in the denominator of Eqn.
(1). Also, the transfer function exhibits a zero given by ω
Z
= g
m/
C
GD,
located in right
half plane. C
GD
creates a feed forward path from the input to the output at high
frequencies, causing distortion in the output.
3
Proposed Architecture
The above mentioned issues because of miller capacitance can be resolved if source
coupled pair is used instead of common source amplifier in half circuit. This
architecture not only avoids input-output coupling, but also reduces the input
capacitance, thereby increasing the maximum frequency of operation. Figure 4 shows
the proposed architecture, which is two source coupled (or differential) amplifiers
connected to provide a differential input and a differential output. One of the inputs of
each differential amplifier (gates of M
2
and M
3
) are connected to a 'dc' voltage, while
to the other (Gates of M1 and M4), the differential input signals are applied. The
outputs are taken at the drains of M2 and M3. When used as a buffer, for the case
when the input voltage of M
1
goes high, M
2
is turned off, the entire tail current
switches to M
1
, and the output voltage at the drain of M
2
becomes V
DD
.
Simultaneously, the input at the gate of M
4
will go low, thus turning off M4, and the
entire tail current of that differential pair flows through M
3
, causing the drain of M
3
to
be at (V
DD
- I
SS
R
D
). Thus the differential output voltage of the circuit will be I
SS
R
D.
Fig. 3.
Proposed Architecture
For this architecture approximate expressions for the dominant pole (ω
p1
), and the
first non-dominant pole (ω
p2
), for a differential input voltage, are found to be:
