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A Novel Input Capacitance Modeling Methodology
for Nano-Scale VLSI Standard Cell Library
Characterization
Akhtar W. Alam, Esakkimuthu Dhakshinamoorthy,
Prince Mathew, and Narender Ponna
ARM Embedded Technologies, Bangalore, India
{Akhtar.alam,Esakkimuthu.Dhakshina,Narender.Ponna,
Prince.Mathew}@arm.com
Abstract.
As the technology scales to 55nm and below, the traditional
modeling methodology of input capacitance results in high deviation between
the back-annotated delay values and the measured delay in Silicon. To reduce
such a high deviation, novel modeling methodologies of input capacitance have
been proposed in this paper. The proposed model have been used across
different process and technology nodes using different test cases and back-
annotated delay values were shown to have good agreement with the measured
delay in Silicon. The proposal can be used to understand the device behavior;
and based on device behavior; the methodology can be used to model the input
cap accurately.
Keywords:
pin capacitance, input cap, hspice, silicon, correlation.
1
Introduction
In this paper we talked about the basic method of improving the Silicon Vs STA
(Static Timing Analysis) correlation [6]. As technology advances, the integration
scale is shooting up. The timing constraint of a design has become very critical hence
the redundant design margin need to be reduced to get better performance. To close
any design, STA is the only viable method for chip-level timing analysis and
therefore its accuracy should be of up most important.
There are many factors that affect the accuracy of STA. Among them, the input
capacitance modeling of logic gates is an important factor because a significant
amount of load capacitance is still occupied by the input capacitances of gates except
for interconnects dominated sections such as clock trees and busses. In STA, the input
capacitance of a gate is modeled as a lumped capacitance. There are a few papers that
explain the importance of the capacitance modeling [1]-[4]. However, no paper has
justified about choosing Max cap or average cap. Also, no paper has studied the input
capacitance variation across different bias condition of PMOS and NMOS device.
Also, although Synopsys Siliconsmart for library characterization measure input
capacitance different input slew and output load condition [5], it is common to
measure capacitance from 20% to 80% rise of input-signal. And among all measured
