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value of cap, the Siliconsmart picks the max or min or average capacitance in a timing
library. In case of max-cap, the STA can predict the longest delay without optimism
so that we can safely check set-up constraints. On the other hand, if we want to
analyze the shortest-path delay, the resulting timing is overestimated and there is a
possibility of existing shorter delays, which will lead to hold violations.
In case of average-cap, the STA can predict the longest delay with some optimism
in critical path; which can cause silicon failure. This paper talked about how to
reduced pessimism and optimism in input pin capacitance measurement.
1.1
Input Pin Capacitance: HSPICE vs STA
STA reads input pin capacitance from the Liberty to calculate corresponding output
delay and slew. As the liberty has only one static value of input pin capacitance, STA
takes total FO cap and uses it to map the delay. In general Liberty takes average value
of input pin capacitance calculated across different condition (from 20% to 80% input
slew). As FO increase, the inaccuracy gets multiplied. To evaluate the discrepancy
between actual gate cap and the gate cap seen by STA, an experiment is done on RO
shown in Figure 1, it is found that the input-cap at nodes net1, net2, net3, … is always
more than the input pin capacitance calculated by STA at these nets. This gives basic
reason of miscorrelation of HSPICE vs STA.
Fig. 1.
Figure 5 show input pin capacitance measured at each nets of the circuit shown in
Figure 1. The capacitance in Liberty [5], which is based on average capacitance
across different input slew and output load, is always less than the capacitance
estimated by HSPICE simulation. SiliconSmart, the characterization tool, have option
to choose range of integration for input pin cap. Default range is 20-80. However, for
given range, the tool calculates the input pin capacitance for combination of
slew/load.
1.2
Variation in Input Pin Capacitance
To study the input pin capacitance very closely, we have devised a method to estimate
the instantaneous capacitance at each instance of input rise/fall. Figure 2 shows the
