Information Technology Reference
In-Depth Information
The
Fig. 4
gives Sum1, Sum2 and Square root entities. The Bi-diagonalization
entity (and SVD) is based on these entities. For Sum2 and Square root entities we use
two multipliers (floating point) and there by introducing parallelism in operations.
Fig. 4.
(a) Sum1 (a) Sum2 (c) Square Root
3.2
Implementation
We have implemented and synthesized L
1
norm of vector, L
2
norm of vector, Bi-
diagonalization of matrix, Sum1, Sum2, Square root. The Bi-diagonalization entity
uses Sum1 and Squareroot entities and other FP core entities. The architectural
entities are implemented and synthesized on Xilinx Artix-7 with ISE-14.x and the
implementation is done in VHDL. The Floating Point core (FP) 6.0 is used.
The Xilinx FP Core (blocking mode) gives the results of calculation after certain
duration. The duration is multiple (N) of clock cycles for operations like Multiply,
ADD/SUB, DIV etc.
We have implemented following techniques:
•
For repetitive operations, 'for loop' i.e. for functional we have provided a
control flag (gated if with clock) which controls the execution to next stage.
The flag is updated when all the required operations are done in each of the
iteration.
•
Wait for the floating point operations is implemented by using a variable to
count the desired number of cycles on clock along with a flag whether to
proceed to next stage or not.
•
We have used above techniques for creating L1 norm of vector, L2 norm of
vector, Bi-diagonalization of matrix synthesizable entities.
The
Fig. 1
gives RTL view of L
1
norm of vector and L
2
norm of vector. The
memory module uses LogiCore to define memory. The controller interacts with L
1
norm entity and L
2
norm entity. The controller along with memory module gets data
in/out for processing.
The
Fig. 2
gives the brief overview of Bi-diagonalization. It indicates that there are
multiple loops and nested loops along with conditional checks. The design decision to
create the entities like Sum1, Sum2 and Squareroot and techniques enabled us to
create synthesizable entity for Bi-diagonalization.
