Information Technology Reference
In-Depth Information
We also have done VHDL implementation of SVD using Bi-diagonalization entity
and other entities as shown in
Fig. 3
. The memory module uses LogiCore to define
memory. The controller interacts with Bi-diagonalization entity and QR module. The
controller along with memory module gets data in/out for processing. The QR
algorithm is part of test code and uses Sum2 and other FP components. We have
tested the output of SVD and verified against matlab. For the cases when rows are
less than columns for a matrix A, the SVD of the A
T
is to be computed initially and
then perform interchanges U and V which can be part of testcode.
4
Results
The scheme has been tested using Xilinx Artix-7 with ISE-14.x and FP core 6.0. The
test input given to the system was random. The device summary details are also
given below for various synthesized entities.
L
1
Norm:
We have implemented L
1
norm for various vector sizes. This can be configured as per
user need. We verified the output of L
1
norm using matlab as reference output and no
error was observed. The time to compute L
1
norm for few vector lengths is given
below and the time scales in proportion of the length.
Vector Lengths
Time
10, 100
1.305 us, 13.005 us
L
2
norm:
We have implemented L
2
norm for various vector sizes. This can be configured as per
user need. We verified the output of L
2
norm using matlab as reference output and no
error was observed. The time to compute L
2
norm for few vector lengths is given
b
elow and the time scales in proportion of the length.
Vector Lengths
Time
100, 49
23.695 us, 11.969 us
Bi-diagonalization:
We have implemented Bi-diagonalization and verified its output with the reference
software implementation and the results were matching. The timing for a matrix size
is given below and found to be acceptable
for SVD implementation.
Matrix
Time
4X4
24.915 us
Device Summary for L
1
Norm of Vector and L
2
Norm of Vector and
Bi-diagonalization:
Selected Device: xa7a100tcsg324-2i.
