A Methodology for Early and Accurate Analysis of Inrush and Latency Tradeoffs during Power-Domain Wakeup - VLSI Design and Test - page 296

In this picture, VDDSW is the switched power-rail, while VDDC is the constant-
ON power-rail. When a domain wakes-up, VDDSW rises while VDDC sees a
transient drop due to inrush current. The LDO senses the drop and it will slowly begin
to supply additional current to charge the domain. However, the reaction times of
LDOs are of the order of microseconds, and an LDO cannot react fast enough to
counter the drop due to the inrush current which often peaks within tens of
nanoseconds. Thus the LDO is completely ineffective in guarding against the voltage
dip due to inrush. The instantaneous current is supplied by the on-die and off-die
decoupling capacitors. Hence for the purpose of analyzing the peak voltage-dip due to
inrush, the LDO is good as absent. This is shown in Fig 3 below, which also shows
the charge transfer during domain-wakeup.

Fig. 3. Charge transfer during domain wake-up

3 Limitations of Currently Available Tools/Methodologies

Although several EDA tools are available in the industry to analyze inrush currents
they mostly suffer from two disadvantages.
First, most EDA tools require usage of an ideal-voltage-source as the primary
source in the circuit to be analyzed. This is a major limitation since real-life on-die
LDOs cannot be modeled as ideal voltage sources because (as explained earlier) they
have slow reaction-times : much slower than the rate at which voltage dips due to
inrush current. Usually EDA tools do not provide a way to model this slow-reaction
time.