A Methodology for Early and Accurate Analysis of Inrush and Latency Tradeoffs during Power-Domain Wakeup - VLSI Design and Test - page 297

Second, typical EDA tools that analyze inrush are not suitable for usage during
Architecture stage or early design stages. This is because they require views like DEF
and Timing analysis, which are available quite late in the product development cycle.
On the other hand some information about best latency available is needed during
product-definition/architecture or early-development stage. These limitations prompt
us to find a simple solution that can overcome the two issues above.

4 Modeling

In this section we discuss a methodology for modeling the power-domain system.
The first step is estimating the effective Gate-count (G P ) for each power-domain
(“P”). Gate-count is the equivalent NAND-gates for the domain.

A



G =

i

(1)

p

A

i

NAND

where A i is the area of the i th standard-cell in the power-domain P, and A NAND is the
area of the basic NAND cell in the library.
For simplicity let us assume that only one domain is switching at a time. Let us call
the switching-on domain “S”. The gate count (G p ) for this domain is designated as G S .
The next step is to arrive at an initial estimate on the number of switches “N PS ” in this
power domain. Usually N PS is derived from the peak-current considerations.

I

()

Peak S

N =

(2)

PS

I

MAX _ SS

where I Peak(S) is the peak Active-Mode current requirement of the domain S, and
I MAX_SS is the maximum current that the strong-switch can supply across various
process-temperature corners with a given (low) voltage drop across the switch.
While the domain S switches-ON, other domains which are already ON act
as decoupling capacitors. The gate count of these already-ON domains can be
estimated as -

pL =



G = G

(3)

AON p

p = 1

where p is each domain among L domains that are already on when the domain 'S' is
turning ON.
Thus, we now have a basic switching model for early analysis. The accuracy of this
circuit can be improved by adding information about parasitic-elements like package-
inductance (L P ) and package-resistance (R P ), as well as early estimates of resistance
offered by the power grid-routing (R PR ). The circuit of fig 3 can now be elaborated as
fig 4 below -