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Fig. 1.
Power-switch cell with weak and strong PMOS switches
when the system is dormant-state, but when a request for processing comes, it need to
wake-up quickly from sleep to service the request. In the semiconductor-market,
SoCs for control applications compete with each other on the time it takes them to
wake-up from a standby mode. Since the wakeup-sequence requires charging one or
more power domains to full-rail, the time required for the charging up the domain
becomes a key parameter. In the rest of the discussion we will call this parameter as
“domain charging latency” or just “latency” for short.
From the above discussion it is readily seen that designers are faced with two
mutually contradictory requirements during domain-wakeup: If the domain-charging
is too slow then the latency suffers, while if the domain charging is too fast then
inrush current may cause a dip in the supply voltage, that could be fatal for already-
ON and working domains. Designers need to strike a balance between the two
requirements. The rest of the paper is dedicated to elaborating this issue in the context
of low-power SoCs, and describing a methodology for an early analysis and
resolution of this issue.
2
Power-Supply System in an SOC with on Die LDO
Many SoCs have a built-in on-die Low-drop-out (LDO) voltage regulator, which is
the power supply for the various power-domains. Also, most LDOs use an off-die
capacitor to stabilize their output (labeled 'C
O
' in the fig 2. below).
Fig. 2.
Power-supply system with on-die LDO
