CPK Based IO AC Timing Closure to Reduce Yield Loss and Test Time - VLSI Design and Test - page 260

Table 1. SPI AC Timing Specification of P1020 [1] SoC

symbolizes the NMSI outputs internal timing (NI) for the time tSPI memory clock
reference (K) goes from the high state (H) until outputs (O) are valid (V).
2. Output specifications are measured from the 50% level of the rising edge of
CLKIN to the 50% level of the signal. Timings are measured at the pin.
3. See the P1020 QorIQ Integrated Processor Reference Manual for detail about the
register SPMODE

As an example, Table 1 shows the I/O setup and hold time for SPI interface and
Fig.2 depicts I/O data relationship wrt internal clock of SPI i.e. SPICLK.

3 CPK Description

CPK is calculated using the equation-

Fig. 3. Equation of Coefficient of Process Capability (CPK)

Where, USL & LSL stands for Upper & Lower Specification Limit respectively.
& are the mean and standard deviation of the quality characteristic studied
respectively.