Process Aware Ultra-High-Speed Hybrid Sensing Technique for Low Power Near-Threshold SRAM - VLSI Design and Test - page 6

Fig. 5. Mean and standard deviation of sensing delay variation with supply voltage. Obtained by
Monte Carlo Simulation for 1000 iterations.

Fig. 3. Fig. 3 shows for PDSA that all the samples yield correct result. A typical value
equal to 100fF for bit-line and data-line capacitances is used to account the effect of
large cells of array in bit-line and data-lines at 1V, standard 6T cell with same cell
current (I cell ) is used for all simulations. The problem of variability defined as standard
deviation (˃) and mean (µ). In Fig. 4, Monte Carlo simulation of sensing delay distri-
bution is shown for VMSA, HMSA [10] and PDSA at various voltages. npass signifies
the number of passed samples. Failure analysis is performed only on the sense amplifi-
er stage in all the topologies for 3˃ process variation. A smaller ˃ is a significant bene-
fit for SA robustness against variability. Fig. 4, verify that 18.4% and 19.7% yield
improvement in proposed design from VMSA and HMSA [10] respectively, and pro-
posed design exhibit 39.18% less ˃ than hybrid at 1V depicted by Fig. 4, although
voltage mode SA has less ˃, but it has lower yield characteristic. Similarly at
V DD =0.9V, ˃ value is 72.96% less compared to HMSA and comparable to VMSA as
shown in Fig. 4. Fig.5 Plots the supply voltage vs mean (ʼ) and standard deviation ( σ ).

Fig. 6. Sensing delay variation with supply voltage Fig. 7. Layout view of

proposed design SA