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3
Noise Cancellation and Topology
Proposed noise cancelling circuit emphasizes the cancellation of n
oi
se generated by
M1. Fig. 4 shows simplified noise cancelling technique in which
,
is
thermally
generated channel noise current equal to
4kTγg
m1
Δf
. Equivalent noise voltage
,
at
the gate of M1 is
4kTγΔf/g
m1
. With respect to this source, we observe a phase shift of
180
o
in noise voltage at node B because of CS stage (source of M1 is common termin-
al) while it is in phase at node A because of source follower stage (drain of M1 is
common terminal). Therefore, noise voltage at node A and at node B becomes 180
o
out
of phase. After that, there is a phase shift of 180
o
between the noise voltages at node A
and node C because of CS stage (M2) and hence the noise voltage at node B and node
C are in phase. This CS amplifier (M2) also amplifies the RF input signal V
s
.
The noise voltage generated by M1 is observed to be in phase at nodes C and D
due to CG stage (M3) while the noise voltage at node E is 180
o
out of phase with
respect to noise voltage at node B due to CS stage (M4). This finally results in noise
voltages at nodes D and E to be 180
o
out of phase and hence is cancelled by adding
them at the output.
Simultaneously, RF input signal is amplified through paths A-C-D and A-B-E and
the phase shift in both these paths are identical. Finally, the amplified RF signal at
node D and E are in phase and hence added at the output through an adder circuit.
Hence this topology amplifies the RF input signal and simultaneously cancels the
noise of most dominating thermally generated noise source.
Noise sources of first two stage components are shown in Fig. 5. Theoretical
values of noise voltages for transistors and resistors are
4kTγΔf/g
mi
and
kT
4 . Where
k
is Boltzmann constant,
T
is absolute temperature,
γ
is transistor parameter,
g
is
transconductance of
i
th
transistor,
R
i
, and
X
i
are equivalent resistor and impedance
associated with
i
th
inductor respectively. In the analysis below, it is assumed that the
noise of M1 is being cancelled and remaining components of first two stages are
contributing to overall noise figure.
Let
and
are noise factors at two different output nodes z and z' as shown in
Fig 5. Equations (3), (4) and (6) are derived for
,
and overall noise factor of the
circuit considering first two stages are having major contribution in noise:
i
Noise power at node z due to
,
2
,
4
,
4
Noise power at node z due to
(1)
F
z
=1+
Noise power at node z' due to
1
,
2
,
3
,
2
Noise power at node z' due to
F
z'
=1+
(2)
R
g
m1
X
2
R
s
R
2
4R
s
R
4
g
m1
g
m4
X
X
4
2
R
γ
g
m1
X
o
2
g
m4
R
ʱ
2
ʱ
2
F
z
= 1+
+
+
+
(3)
