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.i 1
.o 2
.p 14
.s 7
0 START state6 00
0 state2 state5 00
0 state3 state5 00
0 state4 state6 00
0 state5 START 10
0 state6 START 01
0 state7 state5 00
1 state6 state2 01
1 state5 state2 10
1 state4 state6 10
1 state7 state6 10
1 START state4 00
1 state2 state3 00
1 state3 state7 00
Step 2: Boundary depth of the circuit is determined.
First, steady state probability of each state is calculated using
[6]. Boundary depth is taken as 2 for dk27 circuit.
Step 3: Targeting power gated implementation probabilistic
power model is developed.
Step 4: FSM is partitioned and encoded together using Genet-
ic Algorithm taking cost function developed at step 3.
Step 5: Two, 2-level PLA - t1 and t2 are obtained after step 4.
After encoding and partitioning, dk27 benchmark circuit is
divide into two PLA file in SIS tool:
.t0 PLA file- .t1 PLA file-
.i 4 .i 4
.o 5 .o 5
.p 4 .p 4
0011 11000 -110 00010
1000 00100 -1-1 01000
10-1 00010 11-- 00100
-000 10001 -1-- 10000
.e .e
Step 6: Run ESPRESSO [6] for t1 and t2 to get area optimized PLA.
Step 7: Synthesis t1 and t2 in SIS [6] using
lib2-genlib
to get multi-level circuits.
Net list of two PLA file circuit using
lib2-genlib
of SIS [6] tools are obtained. The net
list consists of basic cells- INVERTER, NAND, NOR and DFF.
Step 8: Library development for basic cells like INVERTER, NAND, NOR and DFF
using transistors at TSMC 45nm technology.
Step 9: Basic cells are connected to form F1 (from t1) and F2 (from t2) with the
associated logic for power gated (PG) design.
Step 10: Within_clock_ power_gating concept which is described in [8] is developed
in FSM based power gated design.
Step 11: Within_clock_ power_gating technique inside power gating (WCPG_in_PG)
architecture is implemented in this paper.
The architecture of WCPG_in_PG design of dk27 circuit is shown in Fig. 2.
This architecture is designed and simulated in Cadence Virtuoso Spectre at 45 nm
technology.
Step 12: Simulate the WCPG_in_PG architecture in Cadence Virtuoso Spectre using
45nm TSMC technology.
Step 13: Estimate leakage and dynamic power of combinational and sequential
blocks.
Steps 1 to 5 are executed as in [6]. These steps are followed in the FSM level
targeting power gated design and power is estimated but not actual circuit level
implementation. To get the circuit level implementation of the hypothetical architec-
ture developed in [6], the architecture is modified as in this paper and steps 6 to 9
are followed. Circuit level implementation of within_clock_ power_gating concept
is developed inside power gating technique and architecture of WCPG_in_PG is
implemented in Fig 2 and steps 10 to 13 are followed.
