Power Reduction by Integrated Within_Clock_Power Gating and Power Gating (WCPG_in_PG) - VLSI Design and Test - page 164

of comb1 otherwise it selects the next states of comb2. All the next states propagate
through the original state register at the positive edge of clock and becomes the present
states for the combinational logic after passing through the latch present between
original state register and combinational logic. Present states are inserted into the num-
ber of latches, some of them are connected to the comb1 and the rest are connected to
the comb2. Latch enable signal (lenb) enables and disables the latch depending upon
the MSB bit of the state. When lenb signal is low i.e. MSB bit is '0' then it enables the
latches which are connected to the comb1 and disables remaining latches which are
connected to the comb2. Similarly, reverse process is applicable when MSB bit is '1'.
Initially tenb1 is considered as a low input and tenb2 considered as a high input. MSB
bit of next state, clock signal and tenb1 are inserted into the OR gate, output of which
enables or disables upper high_V T PMOS. Inverted output of MSB bit and clock signal
are inserted into the OR gate, output of this ANDed with tenb2 to enable or disable
lower high_V T PMOS. When MSB bit and tenb1 is '0' at the positive edge of clock,
enbpt0 turns-off the upper high_V T PMOS which power gates the comb1. At the
negative edge of clock, enbpt0 turns-on the upper high_V T PMOS which activates the
comb1 and when MSB bit is '0' and tenb2 is '1' at the positive and negative edge of
clock, enbpt1 disables the lower high_V T PMOS which power gates the comb2 be-
cause there is no states in this sub-FSM. Similarly, When MSB bit and tenb2 is '1' at
the positive edge of clock, enbpt1 turns-off the lower high_V T PMOS which power
gates the comb2. At the negative edge of clock, enbpt1 turns-on the lower high_V T
PMOS which activates the comb2. When MSB bit is '1' and tenb1 is '0' at the positive
and negative edge of clock, enbpt0 disables the upper high_V T PMOS which power
gates the comb2 because there is no states in this sub-FSM. Dynamic power and leak-
age power are reduced in power gated sub-FSM. Leakage power is also reduced in
active sub-FSM so that overall power is reduced. Functions of the other different com-
ponents are as follows:
State Enable Logic. One transmission gate (TG) is used in this logic. Output of this is
controlled by enable signal. Enable signal is chosen in such a way that before applying
clock pulse when it is high, it turns-on the TG then, input passes through the gate
which is considered to be as a present state at initial stage because there is no initial
state After applying clock pulse when enable signal is low, it turns-off the TG then
input does not pass trough gate, so next state is to be considered as a present state.
2:1 Multiplexer. Multiplexer is used to select output from active sub-FSM. MSB bit
is to be considered as select line. When MSB bit is '0', then it selects output from
comb1 because at that instant that machine is in active mode. Similarly when MSB bit
is '1', then it selects output from comb2.
Latch with Enable Signal. At the positive edge of clock signal latch changes its out-
put. Enable signal decides whether state will pass from input to output. Here, MSB bit
of next state is considered to be enable signal. When it is high then it passes the states
otherwise, it disables the latch.

3 Design Flow

Step 1: The circuit in FSM format is taken as input of this architecture. FSM form of
dk27 benchmark circuit is