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sub-FSM is in power gated mode then other sub-FSM is in active mode. At that time in
active sub-FSM, within_clock_ power_gating concept has been used to reduce leakage
power of active sub-FSM. Power will be reduced in active sub-FSM and power gated
sub-FSM so that overall power will be reduced in this proposed architecture. Depending
upon MSB bit of next state code, two enable signals are set in such a way that at a time
one enable signal power gates one sub-FSM and at that moment other enable signal
turns-on other sub-FSM within the clock period at the negative edge of clock.
Works in [5, 6] present partitioning and encoding technique based on genetic
algorithm to divide the states into sub-FSM and to encode the states.
Fig. 1.
Proposed architecture of WCPG_in_PG
For indicating the partition in which a particular state is present, each of state is en-
coded [6] in such a way that if MSB bit is '0', then state is present in upper sub-FSM
(comb1) and if MSB bit is '1' then state is present in lower sub-FSM (comb2). Sleep
transistor is used to power gate each sub-FSM depending on the MSB bit of state. In-
puts are given to both the combinational block. Outputs of the both combinational
blocks are fed into the 2:1 multiplexer. MSB bit of state code is considered as a select
line of multiplexer to select the output from active sub-FSM. Initially, s is considered
as a low input which is given externally. MSB bit of next state and s are fed to the OR
gate, output of which is the select line of multiplexer. If MSB bit is '0' then it
selects the outputs of comb1 because at that time comb1 is in active mode and comb2
is in power down mode and if MSB bit is '1' then it selects the outputs of comb2
which is in active mode. Similarly, when MSB bit is '0' then it selects the next states
