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In-Depth Information
This paper proposes a new architecture which is termed as within_clock_
power_gating inside power gating (WCPG_in_PG) to reduce leakage power of active
sub-FSM and overall power (leakage and dynamic) of inactive sub-FSM.
Leakage
power and average power results by frequency scaling for different input combination
are reported in this paper.
The contributions of this paper as follows:
1.
Here, multi-level implementation has been considered but in [5, 6] the power
estimation is done targeting two-level circuit implementation only.
2.
The final two-level PLA circuit after bipartition in [5, 6] has been taken as the
input circuit in this work for its actual power gated implementation.
3.
The idea of within_clock_ power_gating technique which has been described in [7,
8] has been implemented in active sub-FSM of FSM based power gating technique.
4.
Full custom approach has been adopted for designing each logic block and after
customizing in terms of area, power and noise margin, they are integrated in the
environment of WCPG_in_PG circuit.
5.
In [5, 6], power is estimated at algorithmic level and it only consider dynamic
power of combinational logic but does not care the power of sequential logic.
Here, leakage and dynamic power of all the parts of the architecture such as-
combinational block, sequential blocks, latches and enable logics are considered.
6.
Low power Hybrid latch Flip-Flops which is used as state register, state enable
logic and latch with enable signal, 2:1 multiplexer have been designed. In [5, 6],
all these logic are not implemented.
7.
Leakage and average power results after simulating the proposed architecture in
CADENCE virtuoso spectre at 45 nm technology for different frequency and in-
put combinations have been reported separately and the results of this architec-
ture are compared with FSM based power gating technique, within_clock_
power_gating and no power gating technique.
Rest of paper is organised as follows: proposed architecture and working principle
of WCPG_in_PG
are presented in section 2, design flow of this technique is shown in
section 3, experimental results are reported in section 4 and conclusion and future
scope of this work are described in section 5.
2
Proposed Architecture and Working Principle of
WCPG_in_PG
In this section the proposed architecture for the implementation and working principle
of within clock power gating inside power gating is explained. The proposed architec-
ture of WCPG_in_PG is shown in Fig.1. Here, A FSM is partitioned into two sub-FSM
and states of the FSM are encoded using GA algorithm to achieve power saving. After
partitioning FSM into two sub-FSMs, some states are present in upper sub-FSM and
some states are present in lower sub-FSM. At a time only one of these sub-FSM is ac-
tive and the power supply of the other sub-FSM can be cut off for power saving. A
high_V
T
PMOS is connected between VDD and each of the sub-FSM for achieving low
leakage power which is used to power gate each sub-FSM. Inner transitions occur
within each sub-FSM and Cross transition occurs between the sub-FSMs. When one
