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which increase the SA input offset (due to its differential nature, and small signal
operation) and deteriorates SRAM read access yield (Y
read
) [3], [4], [5]. Hence, the
failure probability of a SA is directly related to the yield of a memory chip. The sens-
ing margin required by SRAM is dominated by the sense amplifier offset and bit-line
(BL) level offset. SA offset is caused by device mismatch resulting from process vari-
ations. Hence SA input referred offset directly slows the access times of SRAMs and
limits the amount of integration of cells on a column.
Substantial amount of research have so far been reported regarding sensing speed
improvement, offset reduction and yield improvement of SA [6-14], like latch based
SA [6], Voltage Mode SA(VMSA) [7], Decoupled latch [8] [9], Hybrid Mode SA
(HMSA) [10], Automatic power down (APD) SA [11], etc. Among the above men-
tioned techniques, voltage & current mode implementations are popular to the re-
searchers, which also serve the limitations. [6], [8] shows the conventional voltage
mode SA The self shut-off mechanism of VSA has made it a pervasive choice in to-
day's SRAM design. The input offset of sense amplifier in voltage mode sets the
higher levels for the required bit-line discharge [8], [12], thereby increasing the ener-
gy consumption. This offset affects the sensing delay or even the functionality of the
circuit, depending on the extent of process variation, therefore determining the worst
case possibility of process variation highly significant in sense amplifier. The minimal
target value of the required bit-line discharge depends on the technology, sense am-
plifier design, sizing and the target yield level [5] [12]. Current sense amplifiers
(CSA) have long been proposed as a promising approach for high speed applications
since they do not require large bit-line voltage swing for detection. The new read
scheme to maximize the utilization of I
cell
, hence offering a better performance in
terms of sensing speed proposed in [10], nevertheless, such hybrid mode sense am-
plifier consumes more power than a typical latch type sense amplifier due to its dc
bias current. On the other hand, the automatic power down scheme was implemented
in parallel [11] fashion, resulted better speed and power with the penalty of hardware
than earlier reported SAs implementation. In this work, a highly robust and novel
Ultra High-Speed (UHS), hybrid current/voltage mode Sense Amplifier (SA) tech-
nique is developed for low power SRAM using 45nm CMOS standard process. This
paper is organized as follows: Section 2 describes the proposed sensing technique and
its operation and Section 3 discusses the impact of process variation, sensing failure
and design yield. Simulation results are discussed and compared in Section 4. Finally,
Section 5 concludes the paper.
2
Proposed Sensing Technique
The Proposed Design Sense Amplifier (PDSA) with simplified read-cycle only mem-
ory system is shown in Fig. 1. The circuit is evaluated in terms of the propagation del-
delay and power dissipation vs supply voltages, process variations and temperature. It
consists of nine PMOS (MP2-MP10) and seven NMOS transistors (MN1-MN7).
MP2-MP5 configures the Current Mode Circuit (CMC) [12]. It has zero input (ideal-
ly) resistance during sensing. This property makes it insensitive to the bit-line capa-
citance. CMC eliminates the bit-line equalization circuit due to virtual short circuit at
