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Process Aware Ultra-High-Speed Hybrid Sensing
Technique for Low Power Near-Threshold SRAM
Bhupendra Singh Reniwal and Santosh Kumar Vishvakarma
Nanoscale Devices, VLSI/ULSI Circuit & System Design Lab Indian Institute of Technology
Indore, India
{phd11120202,skvishvakarma}@iiti.ac.in
Abstract.
Significant speed degradation is one of the severest issues encoun-
tered in low-voltage Static Random Access Memory (SRAM) operation. In
addition, Sense Amplifier (SA) stability deterioration is another problem in
low-voltage operation. These phenomena occur because the random transistor
variation becomes larger as the process scaling progresses. In this work a highly
robust and novel Ultra-High-Speed (UHS) hybrid current/voltage sensing tech-
nique is developed for low power and high speed SRAM. The Precisely sized
Current Mode Circuit (CMC) is designed for local differential current mode
sensing at bit-lines to achieve low power and high-speed. Local cross coupled
inverters latch configuration is designed which convert differential voltage de-
veloped at data-lines to full logic swing at output. High speed SRAM sensing
technique is designed using a 45nm CMOS standard process. With focus on the
current sensing, we have shown that latch makes an excellent second-stage
comparator after a local differential current sensing. Extensive post-layout si-
mulation has been verified that our design operates down to 0.7V and achieves
95ps sensing delay at 1V supply voltage. Operating frequency is 1 GHz and
power consumption is 2.18ʼW and 0.10ʼW at 1V and 0.7V respectively. The
primary advantage of the proposed amplifier over previously reported sense
amplifiers is the excellent immunity to inter-die and intra-die variations, making
it more reliable against device mismatch and process variations.
Keywords:
SRAM, CMC, UHS, Yield, SA.
1
Introduction
In nanometer technologies, embedded SRAM occupy significant portion of system on
chips (SoCs) and has large impact on chip yield. As the motivation to increase the
capacity of on-chip cache, SRAM is predicted to occupy about 94% of die-area by
2014 [1]. Increasing inter-die statistical variations in the process parameters (channel
length (L)
,
width (W), and transistor threshold voltage (V
th
) has emerged as a serious
problem in the nano-scaled circuit design [2]. With the increase in random variation
with scaling due to Random Dopant Fluctuation (RDF), Line Edge Roughness (LER)
and other sources, SRAMs become extremely sensitive to process variations especial-
ly as the supply voltage is reduced. Similarly, SA suffer from random variations,
