A Modified Gate Replacement Algorithm for Leakage Reduction Using Dual-Tox in CMOS VLSI Circuits - VLSI Design and Test - page 152

4 Conclusion

This research paper introduces a modified gate replacement algorithm that uses the
concept of dual- T ox transistors. Using this approach, the normalized delay and leakage
current is analyzed for varying T ox and width of a PMOS transistor. Moreover, the
approach is applied to different ISCAS and ITC'99 benchmark circuits that exhibit an
overall reduction in leakage current by 39.9% as compared to the initial leakage.

References

1. Singh, S., Kaur, B., Kaushik, B.K., Dasgupta, S.: Leakage Current Reduction using
Modified Gate Replacement Technique for CMOS VLSI Circuit. In: Proc. IEEE CODIS
2012, Kolkata, pp. 464-467 (2012)
2. Roy, K., Mukhopadhyay, S., Mahmoodi-Meimand, H.: Leakage current mechanisms and
leakage reduction techniques in deep-sub micrometer CMOS circuits. Proc. of IEEE 91,
305-327 (2003)
3. Mukhopadhyay, S., Roy, K.: Accurate Modeling of Transistor Stacks to Effectively
Reduce Total Standby Leakage in Nano-Scale CMOS Circuits. In: IEEE Int. Symp. VLSI
Circuit Digest, pp. 53-56 (2003)
4. Abdollahi, A., Fallah, F., Pedram, M.: Leakage current reduction in CMOS VLSI circuits
by input vector control. IEEE Trans. Very Large Scale Integration Systems (VLSI) 12,
140-154 (2004)
5. Yuan, L., Qu, G.: A Combined Gate Replacement and Input Vector Control Approach for
Leakage Current Reduction. IEEE Trans. Very Large Integration (VLSI) Systems 14,
173-182 (2006)
6. Jayakumar, N., Khatri, S.P.: A Simultaneous Input Vector Control and Circuit
Modification Technique to Reduce Leakage with Zero Delay Penalty. ACM Transactions
on Design Automation of Electronic Systems (TODAES) 16, 9:1-9:20 (2010)
7. Sultania, A.K., Sylvester, D., Sapatnekar, S.S.: Gate oxide leakage and delay tradeoffs for
Dual- T ox circuits. IEEE Trans. Very Large Integration (VLSI) Systems 13, 1362-1375
(2005)
8. Rabaey, J.M., Chandrakasan, A., Nikolic, B.: Digital integrated circuits. Prentic Hall, New
Jersey (2002)
9. Kang, S.-M., Leblebici, Y.: CMOS Digital Integrated Circuits: Analysis and Design, 3rd
edn. Tata McGraw-Hill Publishers (2002)
10. Gao, F., Hayes, J.P.: Exact and heuristic approaches to input vector control for leakage
power reduction. IEEE Trans. Computer-Aided Design of Integrated Circuits and
Systems 25, 2561-2574 (2006)
11. Chen, Z., Johnson, M., Wei, L., Roy, K.: Estimation of standby leakage power in CMOS
circuits considering accurate modeling of transistor stacks. In: IEEE Int. Symp. Low
Power Electronics and Design (ISLPED 1998), pp. 239-244 (1998)
12. http://www.cad.polito.it/downloads/tools/benchmarks.html
13. http://www.ece.uic.edu/~masud/resources.html