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reduce the leakage of the circuit for all input states. Thus, the modified gate
replacement approach can be applied wherein a two input NAND gate is replaced with
three input NAND gates having higher value of
T
ox
for PMOS transistors. It is observed
that when the sleep signal is low, circuit is in the standby mode. Using this mode, a
drastic reduction in leakage current is observed along with the functionality of the
circuit that is maintained in active mode without significant increase in leakage current.
Table 3.
Leakage current for different input states for a two input NAND gate using
T
ox
variation and stacking effect along with dual-
T
ox
transistors
Input
states
Initial
Leakage(nA)
Leakage
using
T
ox
variation(nA)
Leakage using stacking along with dual-
T
ox
transistors (nA)
Sleep=0
Sleep=1
00
0.786
0.772
0.929
1.104
01
13.262
13.255
0.717
12.391
10
4.850
4.843
0.690
7.432
11
17.161
14.309
6.502
17.052
3.3
Analysis of Leakage Current for Benchmark Circuits
This sub section analyzes the minimum leakage finding technique by using the
modified gate replacement along with dual-
T
ox
PMOS transistors. Different
benchmark circuits of ISCAS and ITC'99 [12, 13] series are used to find the
minimum leakage current. It is observed that the overall leakage of the benchmark
circuits is reduced by 39.9% in standby mode as presented in Table 4 and Fig. 3.
Table 4.
Leakage reduction using modified replacement technique for benchmark circuits
Benchmark circuits
Initial leakage (nA)
Final leakage (nA)
% reduction
C17
61.407
31.604
48.5
B01
606.140
407.66
32.7
B02
439.828
271.20
38.3
B06
902.301
540.77
40.1
900
Initial leakage
Final leakage
800
700
600
500
400
300
200
100
0
C17
B02
B01
B06
Benchmark circuits
Fig. 3.
Leakage current reduction for different Benchmark Circuits
