Impact of Fin Width and Graded Channel Doping on the Performance of 22nm SOI FinFET - VLSI Design and Test - page 153

Impact of Fin Width and Graded Channel Doping
on the Performance of 22nm SOI FinFET

Jose Joseph and Rajendra Patrikar

Department of Electronics Engineering
Visvesvaraya National Institute of Technology, Nagpur-440010
[e-mail], [e-mail]

Abstract. The potential impact of fin width and graded channel doping on the
analog performance of 22nm n-channel FinFET are studied using well cali-
brated 3D TCAD simulations. It is ascertained that for FinFETs, lesser the fin
width, better the characteristics. But limitations in lithography process curb the
fin width to be scaled beyond 10nm. Stability of the fins patterned beyond
10nm width is to be viewed with suspected eyes. It is observed that Graded
doping of the channel will improve threshold voltage and hence the ratio of I on
to I off will also increase, which is desired for enhanced performance in analog
applications.

Keywords: FinFET, graded doping, fin width, TCAD.

1 Introduction

FinFET is one of the emerging CMOS devices that use an ingenious architecture al-
lowing better control over short-channel effects (SCE) with the aid of 3D geometry
[1]. The use of metal gates help to adjust the threshold voltage and prevents gate dep-
letion and dopant penetration that frequently appear in the conventional polysilicon
gate architecture [2]. Traditionally, fin channel is selected as undoped to avoid the
device mismatches.
Pertaining to electrostatic integrity of FinFETs, the ratio of the minimum gate
length to the minimum fin width should be larger than 1.5 [3]. Therefore, it could be
said that the minimum feature size in FinFET technology is the fin width, not the gate
length [4]. Narrow fin width devices exhibits better immunity to SCEs and reduced
Subthreshold slope [5]. The absence of body contact for the SOI FinFET puts limita-
tions for threshold voltage tuning and can be accomplished either by complicated gate
metal work function engineering or by channel doping [6]. Doped-channel FinFETs
are suitable for system-on-chip applications requiring multiple threshold voltages on
the same die [7]. In this paper, we try to analyze the performance variations of 22nm
FinFET subjected to different fin widths and graded doping conditions. Critical de-
vice attributes like I on , I off , V T , DIBL, Subthreshold slope etc. are investigated as a
function of fin width and graded doping conditions.