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Thus, if ʼ=2, then the fastest inverter has ʳ=1.414 or approx. 1.4, which can be
seen in table 1. This truth is further verified by simulations. The value of g here
should satisfy the delay constraint to be smallest of its recent neighbors. The simula-
tion results for falling and rising output delays are shown in table 2.
Thus, the value of ʳ for minimum delay of the inverter is 1.4. Using this the logi-
cal effort (g) of the inverter is 0.9714.The result thus obtained is also applied to test
the validity to few other static circuits namely, 2-input NAND gate and 2-input NOR
gate.
Table 2.
Average Delay For Various Value Of Gamma
(ʳ)
ʳ
Falling delay (ps)
Rising delay (ps)
Average delay (ps)
1.0
7.146
17.68
12.41
1.1
7.981
16.85
12.42
1.2
8.794
16.07
12.43
1.3
9.385
15.52
12.45
1.4
9.984
14.87
12.42
1.5
10.56
14.33
12.45
1.6
11.199
13.92
12.55
1.7
11.651
13.42
12.54
1.8
12.17
13.03
12.59
1.9
12.67
12.61
12.64
2.0
13.15
12.35
12.72
The result thus obtained is also applied to test the validity to few other static
circuits. Here we consider only 2-input NAND gate and 2-input NOR gate.
2.2
NAND Gate
In order to calculate the logical effort of a NAND gate, we size the transistors so that
their conductance is the same as the single transistors in a reference inverter. The
PMOS transistors are in parallel so, this remains unchanged. But the NMOS transis-
tors are in series, and must be increased in size so that they have the same conduc-
tance as a single NMOS transistor. We define the amount by which the transistor must
be increased as K
N
, the NMOS transistor conductivity coefficient.
In Logical Effort, Ohm's law is used so that K
N
is 2 for a 2-NAND gate, 3 for a 3-
NAND gate and 4 for a 4-NAND gate. The topic recognizes that this is a simplifica-
tion, because velocity saturation of the carriers means that series combinations of
NMOS transistors are more conductive than a single one.
