Characterization of Logical Effort for Improved Delay - VLSI Design and Test - page 112

Fig. 3. Nand gates matching unit inverter

In a more general case where the NAND gate can have a PMOS and NMOS tran-
sistor ratio of ʳ; the NMOS and PMOS conductivity of ʼ; and the value for K N of the
NAND gates need not be equal to the number of series NMOS transistors. A 2-input
NAND gate with the equivalent drive of an inverter with PMOS to NMOS ratio of ʳ :
1 has PMOS to NMOS ratio as ʳ : K N . This matches the conductivity of the NMOS
transistor of the reference inverter, so that the falling logical effort is given by;

( )

K + γ

(6)

g =

N

d

( )

1 + μ

Fig. 4. Nand gates for shortest falling

Fig. 5. Nand gate for rising delay

For the rising logical effort, we scale the PMOS transistor to ʼ and NMOS transistor
to K N (ʼ/ʳ), such that;