Information Technology Reference
In-Depth Information
Fig. 2.
Inverter for shortest rising delay
The logical effort g is then:
(
)
γ
++ +
1
μμγ
μ
1
2
(4)
g
=
(
)
1
+
In the UMC 90nm, ʳ = 2 has been chosen for the inverters because this represents
a good compromise between speed and balanced rise and fall drive strengths, and also
because it is simple and follows widely used industry practice.
Table 1.
Logical Effort For Various Values Of Gamma (ʳ)
PMOS to NMOS ratio of ʳ
Logical Effort (g)
1.00
1.0000
1.20
0.9778
1.40
0.9714
1.50
0.9722
2.00
1.0000
2.25
1.0230
2.50
1.0500
3.00
1.1100
3.50
1.1700
2.1
How to Get the Fastest Inverter
The logical effort (g) varies as ʳ varies, and we can find the minimum value of g by
differentiating with respect to ʳ and setting the differential to zero.
(
)
γ
++ +
1
μμγ
μ
1
2
g
=
(
)
1
+
(5)
dg
d
2
=−
1
μγ
=
0
γ
γ
=
μ
