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Characterization of Logical Effort for Improved Delay
Sachin Maheshwari
1,*
, Himadri Singh Raghav
2
, and Anu Gupta
1
1
Department of Electrical and Electronics Engineering, BITS, Pilani
{sachin.mahe,himadri.singh.raghav}@gmail.com,
anug@pilani.bits-pilani.ac.in
2
Faculty of Engineering and Technology, MITS Lakshmangarh, India
Abstract.
In this paper, an effort has been made to improve the delay of a gate
by skewing the gates by choosing proper sizing. The expression for skewed log-
ical effort has been derived for universal logic gates namely NOT, NAND and
NOR for minimizing the delay. The validations for minimum delay through si-
mulation was done on a chain of inverters. The improved skewed gates showed
10% - 20% delay reduction on a chain of inverters as compared with normal
skewed gate, high and low skewed gates, whereas, an improvement of 20% -
25% when compared to skewed gates favoring a particular transition. All simu-
lations are done using Spectre in Cadence environment in UMC90nm CMOS
technology at 1V power supply.
Keywords:
Characterization, CMOS technology, delay, logical effort, skewed
gate.
1
Introduction
Modeling and characterization of logic gates has been and still is the subject of nu-
merous works as a critical issue either for delay characterization [1], [2], [3] and op-
timization [4] or to address the robustness related to random process variations in
deep-submicron technologies. In [5], the authors presented an approach based on the
method of logical effort for determining the minimum achievable delay of an imple-
mentation under optimal transistor sizing. While this is a useful metric, it is not suffi-
cient to compare circuits sized to arbitrary (non-minimum) delay points.
In this paper, we have derived the expressions for logical effort of the universal
logic gates, namely NOT, NAND and NOR for minimizing the delay. Before, we
move forward, we have first found the mobility ratio of UMC90nm technology,
which approximately comes out to be 2. Thus, the inverter used as the reference in-
verter is the one with balanced rise and fall drive strengths, so based on the simulation
for equal rise and fall time width of the PMOS and NMOS transistors are chosen.
Then, we explore the effect of shape factor (ʳ), and the mobility ratio (µ), on the logi-
cal effort of gates when to design a gate which favors the important transition. Final-
ly, we have designed the skewed gates which gives the better delay as compared to
*
Corresponding author.
