Performance Analysis of Subthreshold 32-Bit Kogge-Stone Adder for Worst-Case-Delay and Power in Sub-micron Technology - VLSI Design and Test - page 107

5 Conclusion

In this paper, we have analyzed the 32-bit KS adder in sub-threshold region for the
worst-case-delay and power in all five corners and also the corresponding power-
delay product is calculated. To compare the performance of the adder, Spectre simula-
tion in UMC180nm and UMC90nm technology was done. Monte-Carlo simulation is
also done in UMC180nm for checking the reliability of the circuit. There was no error
in the functionality but the delay of the combination circuit got increased from 1.16us
to 1.35us.

Acknowledgments. The authors are grateful to the lab facilities (Oysters Lab) of
Department of Electrical & Electronics Engineering at Birla Institute of Technology
& Science (BITS), Pilani where most of the work has been carried out and is also
thankful to the Department of Electronics & Communication Engineering of Mody
Institute of Technology& Science, Lakshmangarh for the support to finish this work
successfully.

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