AGP - Computer Busses - page 206

Table 11.1 PCI configuration space (Device 0)

Address Reference Register name

00 − 01h VID Vendor identification

02 − 03h DID Device identification

04 − 05h PCICMD PCI command register

06 − 07h PCISTS PCI status register

08h RID Revision identification

0Ah SUBC Subclass code

0Bh BCC Base class code

0Dh MLT Master latency timer

0Eh HDR Header type

10 − 13h APBASE Aperture base address

34h CAPPTR Capabilities pointer

50 − 51h HOST BRIDGECFG Host bridge configuration

53h DBC Data buffering control

55 − 56h DRT DRAM row type

57h DRAMC DRAM control

58h DRAMT DRAM timing

59 − 5Fh PAM[6:0] Programmable attribute map (7 registers)

60 − 67h DRB[7:0] DRAM row boundary (8 registers)

68h FDHC Fixed DRAM hole control

6A-6Bh DRAMXC DRAM extended mode select

6C-6Fh MBSC Memory buffer strength control register

70h MTT Multitransaction Timer

71h CLT CPU latency timer register

72h SMRAM System management RAM control

90h ERRCMD Error command register

91h ERRSTS0 Error status register 0

92h ERRSTS1 Error status register 1

93h RSTCTRL Reset control register

A0 − A3h ACAPID AGP capability identifier

A4 − A7h AGPSTAT AGP status register

A8-ABh AGP Command register

B0-B3h AGPCTRL AGP control register

B4h APSIZE Aperture size control register

B8-BBh ATTBASE Aperture translation table base register

BCh AMTT AGP MTT control register

BDh LPTT AGP low-priority transaction timer register

AGPCMD register

The AGPCMD register reports AGP device capability/status. Its main parameters are:

Address offset A8-ABh

Default value 00000000h

Access Read/write

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