AGP - Computer Busses - page 207

Bit Description

31:10 Reserved.

9 AGP side band enable - 1=enable. 0=disable (Default).

8 AGP enable - 1=enable. 0=disable (Default). When this bit is set to a 0, the

HOST BRIDGE ignores all AGP operations. Any AGP operations received
(queued) while this bit is 1, will be serviced even if this bit is subsequently
reset to 0 . If it is 1, the HOST BRIDGE responds to AGP operations deliv-
ered via PIPE (or responds to the SBA, if the AGP side band enable bit is
set to 1).

7:2 Reserved.

1:0 AGP data transfer rate - One bit in this field must be set to indicate the

desired data transfer rate. Bit 0 identifies × × 1, and bit 1 identifies 2.

11.8.4 AGP memory address ranges
The HOST BRIDGE can be programmed for direct memory accesses of the AGP bus inter-
face when addresses are within the appropriate range. This uses two subranges:

• AMBASE/AMLIMIT - this method is controlled with the memory base register
(AMBASE) and the memory limit register (AMLIMIT).
• APMBASE/APMLIMIT - this method is controlled with the prefetchable memory base
register (APMBASE) and AGP prefetchable memory limit Register (APMLIMIT).

The decoding of these addresses is based on the top 12 bits of the memory base and memory
limit registers which correspond to address bits A[31:20] of a memory address. When ad-
dress decoding, the HOST BRIDGE assumes that address bits A[19:0] of the memory ad-
dress are zero and that address bits A[19:0] of the memory limit address are FFFFFh. This
forces the memory address range to be aligned to 1 MB boundaries and to have a size granu-
larity of 1 MB. The base and limit addresses define the minimum and maximum range of the
addresses.

11.8.5 Graphics aperture
AGP supports a graphic aperture which uses memory-mapped graphics data structures. Its
starting address is defined by APBASE configuration register of HOST BRIDGE and its
range is defined by the APSIZE register, such as 4 MB (default), 8 MB, 16 MB, 32 MB,
64 MB, 128 MB and 256 MB.

11.8.6 AGP address mapping
HOST BRIDGE directs I/O accesses to the AGP port in the address range defined by AGP
I/O address range. This range is defined by the AGP I/O base register (AIOBASE) and AGP
I/O limit register (AIOLIMIT). These are decoded, where the top four bits of the I/O base
and I/O limit registers correspond to address bits A[15:12] of an I/O address. For address
decoding, the HOST BRIDGE assumes that the lower 12 address bits A[11:0] of the I/O base
are zero and that address bits A[11:0] of the I/O limit address are FFFh. This forces the I/O
address range to be aligned to 4 KB boundary and to have a size granularity of 4 KB.