AGP - Computer Busses - page 205

PCI bus configuration mechanism
The PCI bus has a slot based configuration space which allows each device to contain up to
eight functions, with each function containing up to 256, 8-bit configuration registers.
PCI configuration is achieved with two bus cycles: configuration read and configuration
write. A device can be configured using the CONFADD and CONFDATA registers. First a
DWord value is placed into the CONFADD register that enables the configuration
(CONFADD[31]=1), specifies the PCI bus (CONFADD[23:16]), the device on that bus
(CONFADD[15:11]), the function within the device (CONFADD[10:8]). CONFDATA then
becomes a window for which four bytes of configuration space are specified by the contents
of CONFADD. Any read or write to CONFDATA results in the host bridge translating
CONFADD into a PCI configuration cycle.
If the bus number is 0 then a Type 0 configuration cycle is performed on primary PCI
bus, where:
• CONFADD[10:2] (FUNCNUM and REGNUM) are mapped directly to AD[10:2].
• CONFADD[15:11] (DEVNUM) is decoded onto AD[31:16].
The host bridge entity within HOST BRIDGE is accessed as a Device 0 on the primary PCI
bus segment and a virtual PCI-to-PCI bridge entity is accessed as a Device 1 on the primary
PCI bus.
11.8.3 PCI configuration space
HOST BRIDGE is implemented as a dual PCI device residing within a single physical com-
ponent, where:
• Device 0 is the host-to-PCI bridge, and includes PCI bus number 0 interface, main mem-
ory controller, graphics aperture control and HOST BRIDGE's specific AGP control
registers.
• Device 1 is the virtual PCI-to-PCI bridge, and includes mapping of AGP space and stan-
dard PCI interface control functions of the PCI-to-PCI bridge.
Table 11.1 shows the configuration space for Device 0. Corresponding configuration regis-
ters for both devices are mapped as devices residing at the primary PCI bus (bus #0). The
configuration registers layout and functionality for Device 0 is implemented with a high level
of compatibility with a previous generation of PCIsets (i.e., 440FX). Configuration registers
of HOST BRIDGE Device 1 are based on the standard configuration space template of a
PCI-to-PCI bridge.