Information Technology Reference
In-Depth Information
other without the processor being involved. The device that starts the conversion is known as
the initiator and the addressed PCI device is known as the target. The sequence of operation
for write cycles, in burst mode, is:
•
Address phase - the transfer data is started by the initiator activating the
FRAME
signal.
The command is set on the command lines (
C/BE3
-
C/BE0
) and the address/data pins
(
AD31
-
AD0
) are used to transfer the address. The bus then uses the byte enable lines
(
C/BE3
-
C/BE0
) to transfer a number of bytes.
•
The target sets the
TRDY
signal (target ready) active to indicate that the data has on the
AD31
-
AD0
(or
AD62
-
AD0
for a 64-bit transfer) lines is
vali
d. In addition, the initiator indi-
cates its readiness to the PCI bridge by setting the
IRDY
signal (indicator ready) active.
Figure 4.4 illustrates this.
•
The
trans
fer continues using
the b
yte enable lines. The initiator can block transfers if it
sets
IRDY
and the target with
TRDY
.
•
Transfer is ended by deactivating the
FRAME
signal.
The read cycle is similar but the
TRDY
line is used by the target to indicate that the data on
the bus is valid.
Write access
Read access
Data
Data
FRAME
FRAME
PCI device
Target
(addressed
PCI device)
PCI device
Target
(addressed
PCI device)
PCI device
Initiator
(busmaster)
PCI device
Initiator
(busmaster)
TRDY
IRDY
IDRY
TDRY
Indicates that target can
accept data from the bus
Indicates that initiator can
accept data from the bus
Indicates that initiator has
placed valid data on the bus
Indicates that there is
valid data on the bus
Figure 4.4
PCI handshaking
4.2.2 PCI commands
The first phase of the bus access is the command/addressing phase. Its main commands are:
•
INTA sequence - addresses an interrupt controller where interrupt vectors are transferred
after the command phase.
•
Special cycle - used to transfer information to the PCI device about the processor's
status. The lower 16 bits contain the information codes, such as 0000h for a processor
