PCI Bus - Computer Busses - page 106

shutdown, 0001h for a processor halt, 0002h for x86specific code and 0003h to FFFFh
for reserved codes. The upper 16 bits ( AD31 - AD16 ) indicate x86specific codes when the
information code is set to 0002h.
• I/O read access - indicates a read operation for I/O address memory, where the AD lines
indicate the I/O address. The address lines AD0 and AD1 are decoded to define whether
an 8-bit or 16-bit access is being conducted.
• I/O write access - indicates a write operation to an I/O address memory, where the AD
lines indicate the I/O address.
• M emo ry read access - indicates a direct memory read operation. The byte-enable lines
( C/BE3 - C/BE0 ) identify the size of the data access.
• M emo ry write access - indicates a direct memory write operation. The byte-enable lines
( C/BE3 - C/BE0 ) identify the size of the data access.
• Configuration read access - used when accessing the configuration address area of a PCI
unit. The initiator sets the IDSEL line activated to select it. It then uses address bits AD7 -
AD2 to indicate the addresses of the double words to be read ( AD1 and AD0 are set to 0).
The address lines AD10 - AD18 can be used for selecting the addressed unit in a multi-
function unit.
• Configuration write access - as the configuration read access, but data is written from the
initiator to the target.
• Memory multiple read access - used to perform multiple data read transfers (after the ini-
tial addressing phase). Data is transferred until the initiator sets the FRAME s ignal inac-
tive.
• Dual addressing cycle - used to transfer a 64-bit address to the PCI device (normally only
32-bit addresses are used) in either a single or a double clock cycle. In a single clock cy-
cle the address lines AD63 - AD0 contain the 64-bit address (note that the Pentium processor
only has a 32-bit address bus, but this mode has been included to support other systems).
With a 32-bit address transfer the lower 32 bits are placed on the AD31 - AD0 lines, fol-
lowed by the upper 32 bits on the AD31 - AD0 lines.
• Line memory read access - used to perform multiple data read transfe rs (after the initial
addressing phase). Data is transferred until the initiator sets the FRAME s ignal inactive.
• Memory write access with invalidations - used to perform multiple data write transfers
(after the initial addressing phase).
4.2.3 PCI interrupts

The PCI bus support four interrupts ( INTA - INTD ) . The INTA signal can be used by any of
the PCI units, but only a multifunction unit can use the other three interrupt lines ( INTB -
INTD ) . These interrupts can be steered, using system BIOS, to one of the IRQ x interrupts by
the PCI bridge. For example, a 100 Mbps Ethernet PCI card can be set to interrupt with INTA
and this could be steered to IRQ10 .

4.3 Bus arbitration

Busmasters are devices on a bus which are allowed to take control of the bus. For this pur-
pose, PCI uses the REQ (request) and GNT (grant) signals. There is no real standard for this
arbitration, but normally the PCI busmaster activates the REQ signal to indicate a request to