Civil Engineering Reference
In-Depth Information
Fig. 3.20
Single read transaction
3.5.1.3
Single Write Transaction
For a write operation, when the transfer is enabled (Bus2IP_CS = '1' and Bus2IP_
RNW = '0'), the core samples both address and data from the Bus2IP_Addr and
Bus2IP_Data pins, respectively, and IP2Bus_Ack is asserted on a successive clock ris-
ing edge. For a write operation, it should be noted that address on the Bus2IP_Addr bus
and data and Bus2IP_Data bus are assumed to be valid when Bus2IP_CS is asserted.
IP2Bus_Ack is asserted for all write transactions, irrespective of whether the
transaction is valid or not. Successive write operations require that Bus2IP_CS
be de-asserted and reasserted. The timing diagram for a single write transaction is
shown in Fig.
3.21
.
3.5.2
Object Layer
3.5.2.1
Transmit and Receive Messages
Separate storage buffers exist for transmit (TX FIFO) and receive (RX FIFO) mes-
sages through a FIFO structure. The depth of each buffer is individually configu-
rable up to a maximum of 64 messages.
3.5.2.2
TX High-Priority Buffer
The Transfer High-Priority Buffer (TX HPB) provides storage for one transmit
message. Messages written on this buffer have maximum transmit priority. They
are queued for transmission immediately after the current transmission is complete,
pre-empting any message in the TX FIFO.
