Civil Engineering Reference
In-Depth Information
Table 3.1
External I/Os
# IPIC name I/O Default value Description
1 Bus2IP_Reset Input 0 Active high reset
2 Bus2IP_Data(0:31) Input X”00000000” Write Data bus
3 Bus2IP_Addr(0:7) Input “00000000” Address Bus
4 Bus2IP_RNW Input 1 Read or Write signalling
'1' for a Read Trans-
action '0' for a Write
Transaction
5 Bus2IP_CS Input 0 Active high CS
6 IP2Bus_Data(0:31) Output X”00000000” Read Data bus
7 IP2Bus_Ack Output 0 R/W data
acknowledgement
8 IP2Bus_IntrEvent Output 0 Active high interrupt line.
See Note 1.
9 IP2Bus_Error Output 0 Active high R/W error
signal. Reserved for
future use.
10 CAN_PHY_TX Output 1 CAN bus transmit signal
to PHY
11 CAN_PHY_RX Input 1 CAN bus receive signal
from PHY
12 CAN_CLK Input 24 MHz oscillator clock
input
13 SYS_CLK Input Input interface clock
Note 1: The Interrupt line is an edge-sensitive interrupt. Interrupts are indicated via the transition
of the interrupt line from logic '0' to logic '1'
IP2Bus_Ack is asserted for all read transactions, irrespective of whether the
transaction is valid or not. Successive read operations require that the Bus2IP_CS
be de-asserted and reasserted. The timing diagram for a single read transaction is
shown in Fig.
3.20
.
It should be noted that
• read transactions from address locations defined as reserved return all '0's on the
IP2Bus_Data bus,
• read transactions from write-only address locations return all '0's on the IP2Bus_
Data bus,
• read transactions from the AFR register when C_CAN_NUM_ACF = 0 return all
'0's on the IP2Bus_Data bus,
• read transactions on the Acceptance Filter ID Register (AFIR) and Acceptance
Filter Mask Register (AFMR) address locations when C_CAN_NUM_ACF = 0
return all '0's on the IP2Bus_Data bus,
• read transactions on any or all of the AFIR and AFMR address locations when
C_CAN_NUM_ACF > 0 return the data that were written to these locations, and
• read transactions on an empty RX FIFO return invalid data.
