Civil Engineering Reference
In-Depth Information
Fig. 3.19
CAN controller block diagram
interfaced to any microcontroller in a stand-alone mode. When coupled with an
on-chip peripheral bus/processor local bus (OPB/PLB) Intellectual Property Inter-
face (IPIF), which attaches to the core through the IPIC interface, the core can be
connected to the MicroBlaze. This allows the core to be used in an Embedded De-
velopment Kit (EDK) environment. Table
3.1
describes the interface signalling of
the CAN controller.
3.5.1.1
Interface Description
The CAN controller supports the following two modes of transfers
• Single read
• Single write
3.5.1.2
Single Read Transaction
For a read operation, when the transfer is enabled (Bus2IP_CS = '1' and Bus2IP_
RNW = '1'), the core samples the address on the Bus2IP_Addr pins and returns
the corresponding read data on the IP2Bus_Data pins. Read data are returned on a
successive clock rising edge, after a wait time. IP2Bus_Ack is asserted when the
data are ready on the IP2Bus_Data pins. For a read operation, it should be noted
that address is assumed to be valid on the Bus2IP_Addr pins when Bus2IP_CS is
asserted and the core samples the address on the next rising edge of SYS_CLK.
