Civil Engineering Reference
In-Depth Information
Fig. 3.21
Single write transaction
3.5.2.3
Acceptance Filters
Acceptance filters sort incoming messages with the user-defined acceptance mask
and ID registers to determine whether to store messages in the RX FIFO, or to
acknowledge and discard them. The number of acceptance filters can be config-
ured from 0 to 4. Messages passed through acceptance filters are stored in the RX
FIFO.
3.5.2.4
Configuration Registers
This module provides access to the registers through the external microcontroller
interface.
Table
3.2
defines the CAN controller configuration registers. Each of these reg-
isters is 32-bit wide and is represented in big endian format. Any read operations to
reserved bits or bits that are not used return '0'. A '0' should be written to reserved
bits and bit fields not used. Writes to reserved locations are ignored.
3.5.3
Transfer Layer
3.5.3.1
Bit Timing Module
The primary functions of the Bit Timing Logic (BTL) module include:
• Synchronizing the CAN controller to CAN traffic on the bus
• Sampling the bus and extracting the data stream from the bus during reception
• Inserting the transmit bit stream onto the bus during transmission
• Generating a sampling clock for the Bit Stream Processor (BSP) module state
machine
