Using a Hardware Description Language - Digital Design of Signal Processing Systems: A Practical Approach - page 74

Concurrent assertion checks the validity of a property. There are several ways to build properties;
these may be compound expressions using logical operators or sequences:

assert property (request && !ready)
An example of a sequence is:

assert property (@posedge clk) req |- > ##[2:5] grant);

) checks on every posedge of clk the assertion of req , and
when it is asserted then the grant must be asserted in 2 to 5 following clock cycles.

Here, the implication operator (|- >

2.9.14 Packages
SV has borrowed the concept of a package from VHDL. By using package , SV can share user-
defined type definitions across multiple modules, interfaces, other programs and packages. The
package can contain, for example, parameters, constants, type definitions, tasks, functions, import
statements from other packages and global variables. Below is an example:

package FSM_types
// global typedef
typedef enum FSM{INVALID, READ, DECODE, EXECUTE, WRITE} pipelines;
bit idle; // global variable initialize to 0
task invalid_cycle (input [2:0] curret_state) //global task
if (current_state == INVALID)
$display( “ invalid state ” );
$finish;
endtask: invalid_cycle
endpackege

2.9.15 Randomization
SV supports unconstrained and constrained random value generation. The function randomize
returns 1 if it successfully generates the constrained random value, otherwise it returns 0 .

bit [15:0] value1, value2;
bit valid;

initial
begin
for(i=0; i < 1024; i++)
valid = randomize (value1, value2);

end

end
The randomization can also be constrained by adding a with clause. The example given above
can be constrained as:

valid = randomize (value1, value2); with (value1>32; value1