Using a Hardware Description Language - Digital Design of Signal Processing Systems: A Practical Approach - page 73

.
.
task CallVeri2 (input int addr2, output int data2);
.
.
endtask
endmodule
TheCfunction functionC is called fromtheSVmodule, and this function further calls funct1
() and funct2() . These two functions use tasks CallVeri1 and CallVeri2 defined in SV:
// required header files
void fuctionC (int rst, ....)
{
.
.
rest = rst;
.
funct1(...);
funct2(...);
.
.
}
void funct1 (void)
{
.
.
CallVeri1(....);
.
}
void funct2 (void)
{
.
.
CallVeri2(....);
.
}
2.9.13 Assertion
Assertion is used to validate the behavior of a design. It is used in the verification module or in an
independent checker module. SV supports two types of assertion, immediate and concurrent. The
immediate assertion is like an if - else statement. The expression in assert is checked for the
desired behavior. If this expression fails, SV provides that one of the three severity system tasks can
be called. These tasks are $ warning ,$ error and $ fatal . The user may also use $ info where
no severity on assertion is required. Below is an example:
assert(value>=5)
else $warning( “ Value above range ” );