Using a Hardware Description Language - Digital Design of Signal Processing Systems: A Practical Approach - page 75

2.9.16 Coverage
The coverage in SV gives a quantitative measure of the extent that the functioning of a DUT is
verified is the simulation environment. The statistics are gathered using coverage groups. With a
coverage group, the user lists variables as converpoints . The simulator collects statistics of the
values these variables take in simulation. The simulator stores the values of these variables in a
coverage database.
module stimulus;
logic [15:0] operand1, operand2;
.
.
covergroup cg_operands @ (posedge clk)
o1: coverpoint = operand1;
o2: coverpoint = operand2;
endgroup : cg_operands
.
.
.
cg_operands cover_ops = new( );
.
endmodule
Each coverage point contains a set of bins. These bins further refine the values the variable takes
for each range.
covergroup cg_operands @ (posedge clk)
o1: coverpoint = operand1 {
bins low = {0,63};
bins med = {64,127};
bins high = {128,255};
}
o2: coverpoint = operand2 {
bins low = {0,63};
bins med = {64,127};
bins high = {128,255};
}
endgroup : cg_operands.
The coverage group can be used inside a module, class or interface.
Exercises
Exercise 2.1
Write RTLVerilog code to implement the design given in Figure 2.21. Generate the appropriate reset
signal for the feedback register used in the design. Develop a test plan and write a stimulus to test the
design for functional correctness. Also write a test case to count the number of cycles it takes for the
register out_reg to overflow for in1 and in2 and sel set to 1 . Also, code the design and
stimulus in SystemVerilog.