Using a Hardware Description Language - Digital Design of Signal Processing Systems: A Practical Approach - page 65

2.9.3.2 Operators

The advanced features in SVenable it to model complex HW features in very few lines of code. For
this, SV supports C-language like constructs such as:

operand 1 OP ¼ operand 2

, , / , % ,

where OP could be þ , >> , << , >>> , <<< , & , | or ^ . For example, x ¼ x þ 3 can be

written as:

x +=3;

SystemVerilog also supports post- and pre- increment and decrement operations þþ x , x ,
x þþ

and x .

2.9.4 for and do-while Loops
SystemVerilog adds C/C þþ type for and do - while loops. An example of the for loop is:

for(i=0, j=0, k=0; i+j+k < 10; i++, j++, k++)

An example of the do-while loop is:

do
begin
if (sel_1 == 0)
continue;
if (sel_2==3) break;
end
while (sel_2==0);
In this code, if sel_1 is zero, continue makes the program jump to the start of the loop at do .
When sel_2 is 3, break makes the program exit the do - while loop, otherwise the loop is
executed until the time sel_2 is zero.

2.9.5 The always Procedural Block
SV helps in solving the issue of the sensitivity list. There are several variants of the always block
that give distinct functionality for inferring combinational or sequential logic. For a combinational
block, SV provides always_comb . Similarly always_latch infers a latch. and always_ff
realizes synchronous logic:

module adder(input signed [3:0] in1, in2,
input clk, rst_n,
output logic signed [15:0] acc);
logic signed [15:0] sum;

// Combinational block
always_comb
begin: adder
sum = in1 + in2 + acc;
end: adder