Using a Hardware Description Language - Digital Design of Signal Processing Systems: A Practical Approach - page 66

// Sequential block
always_ff @(posedge clk or negedge rst_n)
if (!rst_n)
acc < =0;

else

acc < = sum;

endmodule

2.9.6 The final Procedural Block
The final procedural block is like the initial block in that it too executes only once, but at the
end of the simulation. It is good for displaying a summary of results:

final
begin
$display($time, “ simulation time, the simulation ends\n ” );

end

2.9.7 The unique and priority Case Statements
InVerilog, while synthesizing the code, the user may need to specify the type of logic intended to infer
from a case statement. The synthesis directives full - case and full - case parallel - case
are used to indicate, respectively, whether the user intends the logic to consider the first match it finds
in a case statement if there is a possibility of findingmore than one match, or that the user guarantees
that all cases are handled in the coding and each case will only uniquely match with one of the
selections. This behavior is very specific to synthesis and has no implication on simulation.
SV provides equivalent directives, which are unique and priority , to guarantees the simulation
behavior matches with the intended synthesis results. The examples below explain the two directives:

always @*
unique case (sel) //Equivalent to full-case parallel-case synthesis directive
2'b00: out = in0;
2'b01: out = in1;
2'b10: out = in2;
2'b11: out = in3;
default: out = x;
endcase
The priority case is used in instances where the programmer intends to prioritize the selection
and more than one possible match is possible:

always @*
priority case (1 ' b1) //equivalent to full-case synthesis directive

irq1: out = in0;
irq3: out = in1;
irq2: out = in2;