Using a Hardware Description Language - Digital Design of Signal Processing Systems: A Practical Approach - page 64

or more concisely as:
FA ff (.*, .clk(clk_global), .rest_n (rst_n));
2.9.3 Constructs of the C/C þþ Type
SV supports many C/C þþ constructs for effective modeling.
2.9.3.1 typedef, struct and enum
The constructs typedef , struct and enum of C/C þþ add descriptive power to SV. Their use is
the same as in C. Examples of their use are:
typedef bit [15:0] addr;
typedef struct {
addr src;
addr dst;
bit [31:0] data;
}packet_tcp;
module packet (input packet_tcp packet_in,
input clk,
output packet_tcp packet_out);
always_ff @(posedge clk)
begin
packet_out.dst < = packet_in.src;
packet_out.src packet_in.data;
end
endmodule
The enum construct can be used to define states of an FSM. It can be used in place of the Verilog
parameter or define . The first constant gets a value of 0 . When a value is assigned to some
constant, the following constants in the list are sequentially incremented. For example:
typedef enum logic [2:0]
{idle = 0,
read = 3,
dec, // = 4
exe // = 5} states;
states pipes;
The enum can also be directly defined as:
enum {idle, read=3, dec, exe} pipes;
case (pipes)
idle: pc = pc;
read: pc = pc+1;
.
.
endcase