Using a Hardware Description Language - Digital Design of Signal Processing Systems: A Practical Approach - page 63

Table 2.13 Additional datatypes in SystemVerilog

Data type Description States Example

logic User-defined Four states 0,1, x,z logic [15:0] a,b;

int 32-bit signed Two states 0,1 int num;

bit User-defined Two states 0,1 bit [5:0] in;

byte 8-bit signed Two states 0,1 byte t;

longint 64-bit signed Two states 0,1 longint p;

shortint 16-bit signed Two states 0,1 shortint q;

There are two ways to define an array in SV: packed and unpacked. SystemVerilog can operate on
an entire two-dimensional (2-D) array of packed data, whereas the unpacked arrays can be operated
only on an indexed value. The unpacked 1-D and 2-D arrays are declared as:

bit up_data [15:0];
bit [31:0] up_mem [0:511];
For packed cases the same arrays are declared as:

bit [15:0] p_data;
bit [31:0][0:511] p_mem1, p_mem2;
There are some constraints while operating on packed and unpacked arrays. The unpacked arrays
can be sliced as:

slice_data = up_mem[2][31:15];
// most significant byte at mem location 2

An operator can be applied on an entire packed array of data. An example is:

add_mem = p_mem1 + p_mem2;
Dynamic arrays can also be declared as:

bit [15:0] array[];
array = new[1023];

2.9.2 Module Instantiation and Port Listing
If the same names of ports are used in the instantiated module, the port names can be directly
mentioned using . < name > or can be simply skipped while only ports having different names are
mentioned. Consider a module defined as:

module FA(in1, in2, sum, clk, rest_n);
Assuming the instance has the first three ports with the same name, the instance can be written as:

FA ff (.in1, .sum, .in2, .clk(clk_global), .rest_n (rst_n));