Using a Hardware Description Language - Digital Design of Signal Processing Systems: A Practical Approach - page 55

input c_in,
output c_out);
The parameter values can then be specified using one of the following two options:
adder #(.SIZE1(8), .SIZE2(10)) add_byte
(in1, in2, c_in, sum_byte, c_out);
or, keeping the parameters in the same order as defined:
adder #(8,10) add_byte (in1, in2, c_in, sum_byte, c_out);
2.6.5 Verilog Tasks
Verilog task can be used to code functionality that is repeated multiple times in a module. A task
has input , output and inout and can have its local variables. All the variables defined in the
module are also accessible in the task. The task must be defined in the same module using task and
endtask keywords.
To use a task in other modules, the task should bewritten in a separate file and the file then should
be included using an ' include directive in these modules. The tasks are called from initial or
always blocks or from other tasks in a module. The task can contain any behavioral statements
including timing control statements. Like module instantiation, the order of input , output and
inout declarations in a task determines the order in which they must be mentioned for calling. As
tasks are called in a procedural block, the output must be of type reg , whereas the inputs may be of
type reg or wire . Verilog-2001 adds a keyword automatic to the task to define a re-entrant task.
The following example designs a task FA and calls it in a loop four times to generate a 4-bit ripple
carry adder:
module RCA(
input [3:0] a, b,
input c_in,
output reg c_out,
output reg [3:0] sum
);
reg carry[4:0];
integer i;
task FA(
input in1, in2, carry_in,
output reg out, carry_out);
{carry_out, out} = in1 + in2 + carry_in;
endtask
always@*
begin
carry[0]=c_in;
for(i=0; i < 4; i=i+1)
begin
FA(a[i], b[i], carry[i], sum[i], carry[i+1]);
end
c_out = carry[4];
end
endmodule