Using a Hardware Description Language - Digital Design of Signal Processing Systems: A Practical Approach - page 56

2.6.6 Verilog Functions
Verilog function is in many respects like task as it also implements code that can be called
several times inside a module. A function is defined in the module using function and
endfunction keywords. The function can compute only one output. To compute this output,
the function must have at least one input. The output must be assigned to an implicit variable bearing
the name and range of the function. The range of the output is also specified with the function
declaration. A function in Verilog cannot use timing constructs like # or @ . A function can be called
from a procedural block or continuous assignment statement. It may also be called from other
functions and tasks, whereas a function cannot call a task. A re-entrant function can be designed by
adding the automatic keyword.
A simple example here writes a function to implement a 2:1 multiplexer and then uses it three
times to design a 4:1 multiplexer:
module MUX4to1(
input [3:0] in,
input [1:0] sel,
output out);
wire out1, out2;
function MUX2to1;
input in1, in2;
input select;
assign MUX2to1 = select ? in2:in1;
endfunction
assign out1 = MUX2to1(in[0], in[1], sel[0]);
assign out2 = MUX2to1(in[2], in[3], sel[0]);
assign out = MUX2to1(out1, out2, sel[1]);
endmodule
/* stimulus for testing the module MUX4to1 */
module testFunction;
reg [3:0] IN;
reg [1:0] SEL;
wire OUT;
MUX4to1 mux(IN, SEL, OUT);
initial
begin
IN = 1;
SEL = 0;
#5 IN = 7;
SEL = 0;
#5 IN = 2; SEL=1;
#5 IN = 4; SEL = 2;
#5 IN = 8; SEL = 3;
end
initial
$monitor($time, " %b %b %b\n", IN, SEL, OUT);
endmodule
2.6.7 Signed Arithmetic
Verilog supports signed reg and wire , thus enabling the programmer to implement signed
arithmetic using simple arithmetic operators. In addition to this, function can also return a signed