Using a Hardware Description Language - Digital Design of Signal Processing Systems: A Practical Approach - page 54

Parameters are very handy in enhancing the reusability of the developed modules. A module is
called parametered if it is written in a way that the same module can be instantiated for different
widths of input and output ports. It is always desirable to write parameterized code, though in many
instances it may unnecessarily complicate the coding.
The following example illustrates the usefulness of a parameterized module:
module adder (a, b, c_in, sum, c_out);
parameter SIZE = 4;
input [SIZE-1: 0] a, b;
output [SIZE-1: 0] sum;
input c_in;
output c_out;
assign {c_out, sum} =a+b+c_in;
endmodule
The same module declaration using ANSI-style port listing is given here:
module adder
#(parameter SIZE = 4)
(input [SIZE-1: 0] a, b,
output [SIZE-1: 0] sum,
input c_in,
output c_out);
This module now can be instantiated for different values of SIZE by merely specifying the value
while instantiating themodule. Shown below is a section of the code related to the instantiation of the
module for adding 8-bit inputs, in1 and in2 :
module stimulus;
reg [7:0] in1, in2;
wire [7:0] sum_byte;
reg c_in;
wire c_out;
adder #8 add_byte (in1, in2, c_in, sum_byte, c_out);
.
.
endmodule
In Verilog, the parameter value can also be specified by name, as shown here:
adder #(.SIZE(8)) add_byte (in1, in2, c_in, sum_byte, c_out);
Multiple parameters can also be defined in a similar fashion. For example, for themodule that adds
two unequal width numbers, the parameterized code is written as:
module adder
#(parameter SIZE1 = 4, SIZE2=6)
(input [SIZE1-1: 0] a,
input [SIZE2-1: 0] b,
output [SIZE2-1: 0] sum,