Using a Hardware Description Language - Digital Design of Signal Processing Systems: A Practical Approach - page 53

10 time
units

10 time
units

clk

rst_n

x

y_reg

y 0 y 1 y 2 y 3

0

x

y

y 1 y 2

y 3 x

y 0

Figure 2.16 Timing diagram for the IIR filter design of example 2.9

2.6.4.18 Timing Diagram

In many instances before writing Verilog code and stimuli, it is quite useful to sketch a timing
diagram. This is usually a great help in understanding the interrelationships of different logic blocks
in the design. Figure 2.16 illustrates the timing diagram for the IIR filter design of the pervious
subsection.
A clock is generated with time period of 20 units. The active-low reset is pulled low after 5 time
units and then pulled high after 2 time units. As soon as the reset is pulled low, the y_reg is cleared
and set to 0 . The first posedge of the clock after 10 time units latches the output of the
combinational logic y into y_reg . The timing diagram should be drawn first and then accordingly
coded in stimulus and checked in simulation for validity of results.
All Verilog simulators also provide waveform viewers that can show the timing diagram of
selected variables in the simulation run. Figure 2.17 shows the screen output of thewaveformviewer
of ModelSim simulator for the IIR filter example above.

2.6.4.19 Parameters

Parameters are constants that are local to a module. A parameter is assigned a default value in the
module and for every instance of this module it can be assigned a different value.

x0 1 2 3 4 5 6 7

clk

rst_n
y
y_reg

0
0

1 2 3 4 5 6 7 8 9 10 11 12 13

1 2 4 6 8 10 12

Figure 2.17 Timing diagram from the ModelSim simulator