Using a Hardware Description Language - Digital Design of Signal Processing Systems: A Practical Approach - page 46

2.6.4.9 Conditional Statements

Verilog supports the use of conditional statements in behavioral modeling. The if - else statement
evaluates the expression. If the expression is TRUE it branches to execute the statements in the if
block, otherwise the expression may be FALSE, 0 , x or z , so the statements in else block are
executed. The example below gives a simple use. If the brach_flag is non-zero, the PC is equated
to brach_addr ; otherwise if the brach_flag is 0 , x or z , the PC is assigned the value of
next_addr .

if (brach_flag)
PC = brach_addr

else

PC = next_addr;

The if - (else if) - else conditional statement provides multi-way decision support.
The expressions in if - (else if) - else statements are successively evaluated and, if any of
the expressions is TRUE, the statements in that block are executed and the control exits from
the conditional block. The code below demonstrates the working of multi-way branching using the
if - (else if) - else statement:

always @(op_code)
begin
if (op_code == 2 ' b00)
cntr_sgn = 4 ' b1011;
else if (op_code == 2 ' b01;
cntr_sgn = 4 ' b1110;

else

cntr_sgn = 4 ' b0000;

end

The code successively evaluates the op_code in the order specified in if , else if and else
statements and, depending on the value of op_code , it appropriately assigns value to cntr_sgn .

2.6.4.10 RTL Coding Guideline: Avoid Latches in the Design

A designer must avoid any RTL syntax that infers latches in the synthesized netlist. A latch is a
storage device that stores a value without the use of a clock. Latches are usually technology-specific
and must be avoided in synchronous designs. To avoid latches the programmer must adhere to
coding guidelines.
For decision statements, the programmer should either fully specify assignments or must use a
default assignment. A variable in an if statement in a procedural block for combinational logic
infers a latch if it is not assigned a value under all conditions. This is depicted in the following code:

input [1:0] sel;
reg [1:0] out_a, out_b;
always @ (*)
begin
if (sel == 2 ' b00)
begin
out_a = 2 ' b01;