Using a Hardware Description Language - Digital Design of Signal Processing Systems: A Practical Approach - page 45

These blocks are incorporated in the stimulus module. From the stimulus these signals are input to
the top-level module.

2.6.4.8 Case Statement

LikeC and other high-level programming languages, Verilog supports switch and case statements
for multi-way decision support. This statement compares a value with number of possible outcomes
and then branches to its match.
The syntax inVerilog is different from the format used in C/C þþ . The following code shows the

use of the case statement to infer a 4:1 multiplexer:

module mux4_1(in1, in2, in3, in4, sel, out);
input [1:0] sel;
input [15:0] in1, in2, in3, in3;
output [15:0] out;
reg [15:0] out;
always @(*)
begin
case (sel)
2'b00: out = in1;
2'b01: out = in2;
2'b10: out = in3;
2'b11: out = in4;
default: out = 16'bx;
endcase
end
endmodule

The select signal sel is evaluated, and the control branches to the statement that matches with
this value. When the sel value does not match with any listed value, the default statement is
executed. Two variants of case statements, casez and casex , are used to make comparison
with the 'don't care' situation. The statement casez takes z as don't care, whereas casex takes
z and x as don't care. These don't care bits can be used to match with any value. This provision is
very handy while implementing logic where only a few of the bits are used to take a branch
decision:

always @(op_code)
begin
casez (op_code)
4 ' b1???: alu_inst(op_code);
4 ' b01??: mem_rd(op_code);
4 ' b001?: mem_wr(op_code);
endcase

end

This block compares only the bits that are specified and switches to one of the appropriate tasks.
For example, if the MSB of the op_code is 1 , the casez statement selects the first statement and
the alu_inst task is called.