Digital Design of Communication Systems - Digital Design of Signal Processing Systems: A Practical Approach - page 551

// Write interface to input data memory for in-place computation
.wr_data_o (wr_data_int),
.wr_data_addr_o (wr_data_addr_int),

.wr_data_en_o (wr_data_en_int),

// Read interface to input data memory
.rd_data_i (rd_data_int),

.rd_data_addr_o (rd_data_addr_int),

.rd_key_i (rd_key_int), // Read interface to keys

.rd_key_addr_o (rd_key_addr_int),

// Start signal from the external controller
.start_i ( start_i ),

// Write interface to data FIFO
.wr_ff_data_o (wr_ff_data_int),

.wr_ff_data_en_o (wr_ff_data_en_int),

.wr_ff_data_full (wr_ff_data_full_int),

// Done and output written in FIFO
.ff_data_avail_o (ff_data_avail_o)

);

// Output data FIFO
output_ff output_ff_inst(
.rst

(reset),

.wr_clk (clk),

.rd_clk (clk),

.din (wr_ff_data_int ), // Write interface

.wr_en (wr_ff_data_en_int),

.full (wr_ff_data_full_int),

// Read interface for extranl controller
.dout (rd_ff_data_o),

.rd_en (rd_ff_data_en_i),

.empty (rd_ff_data_empty)

);
endmodule

13.3.3.3 Time-Shared 8-bit Folding Architecture

There is no straightforward method of further folding AES architecture as the algorithm is iterative
and nonlinear while it performs computation for a round. The standard folding techniques covered in
Chapter 8 cannot be directly applied. A trace scheduling technique is used in [32, 33, 38]. In this
technique all the flow of parallel computations in the algorithm are traced. The interdependencies
across these traces are established. All these traces are then folded while taking account of their
interdependencies and then are mapped in hardware.
The processor is designed to use 8-bit data. The architecture implements a 256 AES that requires
14 rounds. The processor uses an 8 240-bit memory for storing cipher and round key. The memory
is managed as i

¼ 0, 1, 2, ... , 14 sections for 15 ARK operations of the algorithm. Each section i