Digital Design of Communication Systems - Digital Design of Signal Processing Systems: A Practical Approach - page 552

(0,0) (0,1) (0,2) (0,3) (0,0) (0,1) (0,2) (0,3)

0 4 8 12 0 4 8 12

(1,0) (1,1) (1,2) (1,3) (1,1) (1,2) (1,3) (1,0)

1 5 9 13 5 9 13 1

(2,0) (2,1) (2,2) (2,3) (2,2) (2,3) (2,0) (2,1)

2 6 10 14 10 14 2 6

(3,0) (3,1) (3,2) (3,3) (3,3) (3,0) (3,1) (3,2)

3 7 11 15 15 3 7 11

(a) (b)

Figure 13.31 State indexing for shift-row operation: (a) original indexing, and (b) shift-row indexing

stores 16 bytes (128-bit) of key for the ith iteration of the algorithm. The ARK block reads
corresponding bytes of the key and the state in each cycle and XORs them. The data is read from
memories in shift-row format, so logic for the SR operation is not required. The block BS is
performed as reading from SBOX ROM.
The technique maps the algorithm on to a byte-systolic architecture. Each iteration of the
implementation reads an 8-bit state directly in row-shifted order. The original indexing of the states
is shown in Figure 13.31(a) and the row-shifted indices are shown in Figure 13.31(b). To access the
values of the states shown column-wise, a simple circular addressing mode is used.
The incremented SR index is generated by implementing a modulo accumulator:

addrSR ¼ðaddrSRþ 5 Þ% 16 :

The %16 is implemented by a 4-bit free-running accumulator that ignores overflows. The same
address is used to index the round key from keymemory. A 4-bit counter roundCount is appended to
the address to identify the round:

addrKey ¼froundCount; addrSMg

where addrKey is the address to the key memory. The design works on reading 8-bit data from the
memory and ciphering the plain text in multiple iterations. Each round of AES requires 16 cycles of
8-bit operations. The design of ARK, SR and BS for 8-bit architecture is shown in Figure 13.32.
The 8-bit result computed from BS is then passed to the mix-column block. The 8-bit design
works on a byte by byte input value from the BS block. The design multiplies each byte with four
constant values inGF(2 8 ) as defined in the standard. The values in the constant matrix are such that
each row has the same values just shifted by one to the right. This multiplication for the first
column is shown here:

2
4

3
5 ¼

2
4

3
5

2
4

3
5 :

C 00
C 01
C 02
C 03

02 03 01 01 C 00

C 01
C 02
C 03

01 02 03 01

01 01 02 03

03 01 01 02